Fast linear phase detector

ABSTRACT

Linear phase detectors comprising circuits ( 1,2 ) receiving reference signals (REF) and first and second clock signals (CLK-Q, CLK-I) for generating first and second (phase) control signals (UP,DOWN) for use in multiplier circuits, demodulators and receivers, have large delays due to long path lengths and many operations between input and output (insight). They can be made faster by providing each circuit ( 1,2 ) with two parallel latches ( 10,11,20,21 ) and a multiplexer ( 12,22 ) for multiplexing latch output signals (basic idea). Said multiplexers generate (frequency control) signals to be supplied to frequency detectors, with a third circuit ( 3 ) generating at least one of said (phase) control signals (UP,DOWN). Said third circuit ( 3 ) comprises a latch ( 30 ) generating said first (phase) control signal (UP), with one of the latches ( 20 ) of the second circuit ( 2 ) generating the second (phase) control signal (DOWN. Or said third circuit ( 3 ) comprises logical circuitry ( 31 - 34 ) comprising four EXOR gates ( 31 - 34 ). A fifth EXOR gate ( 35 ) is used for balancing the third circuit ( 3 ).

The invention relates to a linear phase detector for in response to atleast one reference signal and at least a first and second clock signalgenerating at least a first and second control signal and comprising atleast a first circuit receiving said reference signal and said firstclock signal and a second circuit receiving said reference signal andsaid second clock signal.

The invention also relates to an apparatus comprising a linear phasedetector, and to a method for linearly phase detecting, and to aprocessor program product for linearly phase detecting.

Such a linear phase detector is for example used in an apparatuscomprising for example clock multiplier circuits, phase demodulatorsand/or zero-IF receivers etc. Said linear phase detector controls thephase of a clock (like for example a controlled oscillator) which needsto be synchronized with the reference signal having predictable edgesand for example having a 50% duty cycle. Thereto, said first controlsignal for example comprises an up signal or comprises an error signal,and said second control signal for example comprises a down signal orcomprises a basic (non-error) signal etc.

Said apparatus for example corresponds with a mobile phone, an audioreceiver, an audio/video receiver etc.

A prior art linear phase detector is known from U.S. Pat. No. 5,712,580,which discloses a linear phase detector generating an up signal via afirst D-flip-flop receiving an input signal from a second D-flip-flopsituated in a feedback loop and generating a down signal via a thirdD-flip-flop receiving an input signal from said first D-flip-flop, basedupon quadrature clock signals.

The known linear phase detector is disadvantageous, inter alia, due tobeing slow: said feedback loop, said D-flip-flops each comprising twolatches and the triple D-flip-flop construction necessary for generatingsaid down signal make this linear phase detector unsuitable foroperation at higher frequencies.

It is an object of the invention, inter alia, of providing a fasterlinear phase detector suitable for operation at higher frequencies.

Further objects of the invention are, inter alia, providing anapparatus, a faster method, and a faster processor program product.

The linear phase detector according to the invention for in response toat least one reference signal and at least a first and second clocksignal generating at least a first and second control signal comprisesat least a first circuit receiving said reference signal and said firstclock signal and a second circuit receiving said reference signal andsaid second clock signal, wherein said first and second circuits eachcomprise at least two latches and at least one multiplexer formultiplexing latch output signals, with said linear phase detectorcomprising a third circuit for generating at least one of said controlsignals.

By providing the linear phase detector according to the invention withparallel latches and multiplexers for multiplexing latch output signals,each pair of parallel latches will operate substantially simultaneously,with the multiplexer multiplexing the results from these operations. Asa result, the delay from inputs of said linear phase detector (inputs ofsaid first and/or second circuits) to outputs of said linear phasedetector (outputs of said first and/or second and/or third circuit) isreduced, which makes the linear phase detector faster. Due to outputs ofsaid multiplexers generating (frequency control) signals to be suppliedto for example a frequency detector, said third circuit is necessary forgenerating at least one of said (phase) control signals.

It should be noted that each pair of parallel latches is defined to beparallel due to operating substantially simultaneously (substantially,due to possible different path lengths, different parasitic capacitorsetc.) because of both receiving at least one same input signal (a datasignal or a clock signal etc.) and/or because of both latches supplyingtheir outputs signals to the same multiplexer. So, said pair of latchesreceive at least one same input signal and/or supply their outputsignals to the same multiplexer. Said latches are, in other words,multiplexed latches.

A first embodiment of the linear phase detector according to theinvention is defined by claim 2.

By introducing said third circuit in the form of a latch receiving saidfirst and second clock signal and generating said first control signal,with one of the latches of the second circuit generating the secondcontrol signal, a fast, low complex, low cost and low power consuminglinear phase detector has been constructed.

A second embodiment of the linear phase detector according to theinvention is defined by claim 3.

By supplying said reference signal to at least one control input of saidmultiplexers and to clock inputs of said latches of said first andsecond circuits, with said first clock signal being supplied to at leastone data input of said latches of said first circuit and with saidsecond clock signal being supplied to at least one data input of saidlatches of said second circuit, said linear phase detector can be easilyimplemented in silicon.

A third embodiment of the linear phase detector according to theinvention is defined by claim 4.

By introducing said third circuit in the form of first logical circuitryreceiving the latch output signals of said first circuit for generatingsaid first control signal and comprises second logical circuitryreceiving the latch output signals of said second circuit for generatingsaid second control signal, an even faster (compared to said firstembodiment), low complex, low cost and low power consuming linear phasedetector has been constructed (logical circuitry is faster—has smallerdelays—than latches).

A fourth embodiment of the linear phase detector according to theinvention is defined by claim 5.

By using logical circuitries comprising EXOR gates, said linear phasedetector is of the lowest complexity.

A fifth embodiment of the linear phase detector according to theinvention is defined by claim 6.

By introducing said fifth EXOR gate, the third circuit has beenbalanced, and delays present from inputs of said linear phase detectorto the outputs of said third circuit will be substantially identical,which is advantageous.

A sixth embodiment of the linear phase detector according to theinvention is defined by claim 7.

By supplying said reference signal to at least one control input of saidmultiplexers and to clock inputs of said latches, with said first clocksignal being supplied to at least one data input of said latches of saidfirst circuit and with said second clock signal being supplied to atleast one data input of said latches of said second circuit, said linearphase detector can be easily implemented in silicon.

It should further be noted that prior art non-linear phase detectorsexist comprising multiplexed parallel latches. However, firstly, saidprior art phase detectors are non-linear phase detectors, and secondly,in said prior art non-linear phase detectors, said control signals aregenerated in response to data signals having unpredictable edges. Thecontrol signals in the phase detectors according to the invention aregenerated in response to reference signals having predictable edges (andfor example 50% duty cycles). Thirdly, in said prior art phase detectorsat least one control signal originates from (or is derived from) anmultiplexer output signal, where the control signals in the phasedetectors according to the invention are generated sooner (before themultiplexers are involved). This all results in said prior artnon-linear phase detectors operating completely differently.

Embodiments of apparatus according to the invention, of the methodaccording to the invention and of the processor program productaccording to the invention correspond with the embodiments of the linearphase detector according to the invention.

The invention is based upon an insight, inter alia, that, generally,delay depends upon path lengths present from input to output and uponthe number of operations performed between input and output, and isbased upon a basic idea, inter alia, that, in a linear phase detector, apair of parallel latches plus multiplexer per circuit will minimize thisdelay (minimum path length and minimum number of operations).

The invention solves the problem, inter alia, of providing a fasterlinear phase detector, and is advantageous, inter alia, in that such afaster linear phase detector can operate at higher frequencies, wherebysaid linear phase detector can be further improved by introducing lowcomplex, low cost and low power consuming embodiments for said thirdcircuit

These and other aspects of the invention will be apparent from andelucidated with reference to the embodiments(s) described hereinafter.

FIG. 1 illustrates in block diagram form a linear phase detectoraccording to the invention comprising a latch for generating a controlsignal,

FIG. 2 illustrates in block diagram form a timing diagram for saidlinear phase detector shown in FIG. 1 in case of a first clock signalCLK-Q being early,

FIG. 3 illustrates in block diagram form a timing diagram for saidlinear phase detector shown in FIG. 1 in case of a first clock signalCLK-Q being in phase,

FIG. 4 illustrates in block diagram form a timing diagram for saidlinear phase detector shown in FIG. 1 in case of a first clock signalCLK-Q being late,

FIG. 5 illustrates in block diagram form a linear phase detectoraccording to the invention comprising first and second logical circuitryfor generating control signals,

FIG. 6 illustrates in block diagram form a timing diagram for saidlinear phase detector shown in FIG. 5 in case of a first clock signalCLK-Q being early,

FIG. 7 illustrates in block diagram form a timing diagram for saidlinear phase detector shown in FIG. 5 in case of a first clock signalCLK-Q being in phase, and

FIG. 8 illustrates in block diagram form a timing diagram for saidlinear phase detector shown in FIG. 5 in case of a first clock signalCLK-Q being late.

The linear phase detector according to the invention shown in FIG. 1comprises a first circuit 1 with a latch 10 receiving at its data inputs(with the upper being the normal data input and with the lower being theinverted data input) the first clock signals CLK-Q and receiving at itsrespective clock inputs (with the left clock input being the normalclock input and with the right clock input being the inverted clockinput) the reference signals REF. A normal output (the upper output) oflatch 10 is coupled to a first normal input of a multiplexer 12, and aninverted output (the lower output) of latch 10 is coupled to a firstinverted input of multiplexer 12.

Circuit 1 further comprises a latch 11 receiving at its data inputs(with the upper being the normal data input and with the lower being theinverted data input) the first clock signals CLK-Q and receiving at itsrespective clock inputs (with the left clock input being the normalclock input and with the right clock input being the inverted clockinput) the reference signals REF, compared to latch 10, exchangedconnections. A normal output (the lower output) of latch 11 is coupledto a second inverted input of multiplexer 12, and an inverted output(the higher output) of latch 11 is coupled to a second normal input ofmultiplexer 12.

Multiplexer 12 receives at its control inputs (with the upper being thenormal control input and with the lower being the inverted controlinput) said reference signals REF via, compared to latch 10,non-exchanged connections, and generates at its outputs a firstfrequency control signal destined for a frequency detector.

The linear phase detector according to the invention shown in FIG. 1further comprises a second circuit 2 with a latch 20 receiving at itsdata inputs (with the upper being the normal data input and with thelower being the inverted data input) the second clock signals CLK-I andreceiving at its respective clock inputs (with the left clock inputbeing the normal clock input and with the right clock input being theinverted clock input) the reference signals REF via, compared to latch10, exchanged connections. A normal output (the upper output) of latch20 is coupled to a first normal input of a multiplexer 22, and aninverted output (the lower output) of latch 20 is coupled to a firstinverted input of multiplexer 22. Further, at its outputs, latch 20generates the second (phase) control signal DOWN.

Circuit 2 further comprises a latch 21 receiving at its data inputs(with the upper being the normal data input and with the lower being theinverted data input) the second clock signals CLK-I via, compared tolatch 20, exchanged connections, and receiving at its respective clockinputs (with the left clock input being the normal clock input and withthe right clock input being the inverted clock input) the referencesignals REF via, compared to latch 20, exchanged connections. A normaloutput (the lower output) of latch 21 is coupled to a second invertedinput of multiplexer 22, and an inverted output (the higher output) oflatch 21 is coupled to a second normal input of multiplexer 22.

Multiplexer 22 receives at its control inputs (with the upper being thenormal control input and with the lower being the inverted controlinput) said reference signals REF via, compared to latch 20,non-exchanged connections, and generates at its outputs a secondfrequency control signal destined for a frequency detector.

The linear phase detector according to the invention shown in FIG. 1further comprises a third circuit 3 comprising a latch 30 receiving atits data inputs (with the upper being the normal data input and with thelower being the inverted data input) the second clock signals CLK-I via,compared to latch 20, non-exchanged connections, and receiving at itsrespective clock inputs (with the left clock input being the normalclock input and with the right clock input being the inverted clockinput) the first clock signals CLK-Q via, compared to latch 10,non-exchanged connections. Further, at its outputs, latch 30 generatesthe first (phase) control signal UP.

The timing diagrams of the linear phase detector illustrated in FIG. 1are shown in FIGS. 2, 3 and 4 respectively in case of a first clocksignal CLK-Q being early, in phase and late respectively, with REF beingthe reference signal, with CKQ being the first clock signal, with CKIbeing the second clock signal, with DOWN being the second (phase)control signal, with UP being the first (phase) control signal, and withCP being the difference between said first and second (phase) controlsignal.

The linear phase detector according to the invention shown in FIG. 5comprises first circuit 1 and second circuit 2 already described forFIG. 1, and comprises third circuit 3 now comprising a first logicalcircuitry 31,32,35 with at least first and second EXOR gate 31 and 32,and preferably fifth EXOR gate 35, and comprising a second logicalcircuitry 33,34 comprising at least third and fourth EXOR gate 33 and34.

EXOR gate 31 receives signals V and W being the output signals oflatches 10 and 11. EXOR gate 33 receives signals X and Y being theoutput signals of latches 20 and 21. EXOR gate 32 receives the outputsignals from EXOR gate 31 and from EXOR gate 32 and generates said first(phase) control signal UP. EXOR gate 34 receives the output signals fromEXOR gate 33 and receives a “1” signal (from a source like for example avoltage supply etc.) and generates said second (phase) control signalDOWN. EXOR gate 35 receives the outputs signals from EXOR gate 31receives a “1” signal (from a source like for example a voltage supplyetc.), just for balancing said third circuit 3: for example when lookingforward from each one of the outputs of EXOR gates 31 and 33, the sameimpedance of two parallel inputs of two different EXOR gates can befound. This results in delays in both the UP path and the DOWN pathbeing substantially identical, which is advantageous.

The timing diagrams of the linear phase detector illustrated in FIG. 5are shown in FIGS. 6, 7 and 8 respectively in case of a first clocksignal CLK-Q being early, in phase and late respectively, with REF beingthe reference signal, with CKQ being the first clock signal, with CKIbeing the second clock signal, with DOWN being the second (phase)control signal, with UP being the first (phase) control signal, and withCP being the difference between said first and second (phase) controlsignal.

The linear phase detectors shown in FIGS. 1 and 5 have doubleconnections to fulfil the so-called balanced situation. But theinvention is not limited to this balanced situation and can be used inthe so-called unbalanced situation as well, with single connections.

The expression “for” in “for K” and “for L” does not exclude that otherfunctions “for M” etc. are performed as well, simultaneously or not. Theexpressions “X coupled to Y” and “a coupling between X and Y” and“coupling/couples X and Y” etc. do not exclude that an element Z is inbetween X and Y. The expressions “T comprises Q” and “T comprising Q”etc. do not exclude that an element R is comprised/included as well.

It should be noted that the above-mentioned embodiments illustraterather than limit the invention, and that those skilled in the art willbe able to design many alternative embodiments without departing fromthe scope of the appended claims. In the claims, any reference signsplaced between parentheses shall not be construed as limiting the claim.Use of the verb “comprise” and its conjugations does not exclude thepresence of elements or steps other than those stated in a claim. Thearticle “a” or “an” preceding an element does not exclude the presenceof a plurality of such elements. The invention may be implemented bymeans of hardware comprising several distinct elements, and by means ofa suitably programmed computer. In the device claim enumerating severalmeans, several of these means may be embodied by one and the same itemof hardware. The mere fact that certain measures are recited in mutuallydifferent dependent claims does not indicate that a combination of thesemeasures cannot be used to advantage.

The invention is based upon an insight, inter alia, that, generally,delay depends upon path lengths present from input to output and uponthe number of operations performed between input and output, and isbased upon a basic idea, inter alia, that, in a linear phase detector, apair of parallel latches plus multiplexer per circuit will minimize thisdelay (minimum path length and minimum number of operations).

The invention solves the problem, inter alia, of providing a fasterlinear phase detector, and is advantageous, inter alia, in that such afaster linear phase detector can operate at higher frequencies, wherebysaid linear phase detector can be further improved by introducing lowcomplex, low cost and low power consuming embodiments for said thirdcircuit

1. Linear phase detector for in response to at least one referencesignal (REF) and at least a first (CLK-Q) and second (CLK-I) clocksignal generating at least a first (UP) and second (DOWN) control signaland comprising at least a first circuit (1) receiving said referencesignal (REF) and said first clock signal (CLK-Q) and a second circuit(2) receiving said reference signal (REF) and said second clock signal(CLK-I), wherein said first and second circuits (1,2) each comprise atleast two latches (10,11,20,21) and at least one multiplexer (12,22) formultiplexing latch output signals, with said linear phase detectorcomprising a third circuit (3) for generating at least one of saidcontrol signals (UP,DOWN).
 2. Linear phase detector according to claim1, wherein said third circuit (3) comprises a latch (30) receiving saidfirst (CLK-Q) and second (CLK-I) clock signal and generating said firstcontrol signal (UP), with one of the latches (20) of the second circuit(2) generating the second control signal (DOWN).
 3. Linear phasedetector according to claim 2, wherein said reference signal (REF) issupplied to at least one control input of said multiplexers (12,22) andto clock inputs of said latches (10,11,20,21) of said first (1) andsecond (2) circuits, with said first clock signal (CLK-Q) being suppliedto at least one data input of said latches (10,11) of said first circuit(1) and with said second clock signal (CLK-I) being supplied to at leastone data input of said latches (20,21) of said second circuit (2). 4.Linear phase detector according to claim 1, wherein said third circuit(3) comprises first logical circuitry (31,32) receiving the latch outputsignals of said first circuit (1) for generating said first controlsignal (UP) and comprises second logical circuitry (33,34) receiving thelatch output signals of said second circuit (2) for generating saidsecond control signal (DOWN).
 5. Linear phase detector according toclaim 4, wherein said first logical circuitry (31,32) comprises at leasta first (31) and second (32) EXOR gate, the first EXOR gate receivingsaid latch output signals from said first circuit (1), the second EXORgate (32) receiving output signals from said first EXOR gate (31) andfrom a third EXOR gate (33) for generating said first control signal(UP), with said second logical circuitry (33,34) comprises at least saidthird (33) and a fourth (34) EXOR gate, the third EXOR gate (33)receiving said latch output signals from said second circuit (2), thefourth EXOR gate (34) receiving output signals from said third EXOR gate(33) and from a source for generating said second control signal (DOWN).6. Linear phase detector according to claim 5, wherein said firstlogical circuitry (31,32,35) comprises a fifth EXOR gate (35) receivingsaid output signals from said first EXOR gate (31) and from a source forbalancing said third circuit (3).
 7. Linear phase detector according toclaim 6, wherein said reference signal is supplied to at least onecontrol input of said multiplexers (12,22) and to clock inputs of saidlatches (10,11,20,21), with said first clock signal being supplied to atleast one data input of said latches (10,11) of said first circuit (1)and with said second clock signal being supplied to at least one datainput of said latches (20,21) of said second circuit (2).
 8. Apparatuscomprising a linear phase detector for in response to at least onereference signal (REF) and at least a first (CLK-Q) and second (CLK-I)clock signal generating at least a first (UP) and second (DOWN) controlsignal and comprising at least a first circuit (1) receiving saidreference signal (REF) and said first clock signal (CLK-Q) and a secondcircuit (2) receiving said reference signal (REF) and said second clocksignal (CLK-I), wherein said first and second circuits (1,2) eachcomprise at least two latches (10,11,20,21) and at least one multiplexer(12,22) for multiplexing latch output signals, with said linear phasedetector comprising a third circuit (3) for generating at least one ofsaid control signals (UP,DOWN).
 9. Method for linearly phase detectingthrough in response to at least one reference signal (REF) and at leasta first (CLK-Q) and second (CLK-I) clock signal generating at least afirst (UP) and second (DOWN) control signal and comprising a first stepof receiving said fist clock signal (CLK-Q) and a second step ofreceiving said second clock signal (CLK-I) and a third step of receivingsaid reference signal (REF), wherein said method comprises a fourth stepof latching said reference signal (REF) and one of said clock signals(CLK-Q) and of multiplexing latched signals and a fifth step of latchingsaid reference signal (REF) and the other one of said clock signals(CLK-I) and of multiplexing latched signals and a sixth step ofgenerating at least one of said control signals (UP,DOWN).
 10. Processorprogram product for linearly phase detecting through in response to atleast one reference signal (REF) and at least a first (CLK-Q) and second(CLK-I) clock signal generating at least a first (UP) and second (DOWN)control signal and comprising a first function of receiving said firstclock signal (CLK-Q) and a second function of receiving said secondclock signal (CLK-I) and a third function of receiving said referencesignal (REF), wherein said processor program product comprises a fourthfunction of latching said reference signal (REF) and one of said clocksignals (CLK-Q) and of multiplexing latched signals and a fifth functionof latching said reference signal (REF) and the other one of said clocksignals (CLK-I) and of multiplexing latched signals and a sixth functionof generating at least one of said control signals (UP,DOWN).